Non-volatile memories and memory devices are well known in the art. Referring to FIG. 1 there is shown a schematic block level diagram of a memory device 10 of the prior art. The device 10 comprises well known components such as an address controller 12 for receiving address signals from an address bus 14. The address signals are supplied to an X decoder 16, also commonly known as a row or word line decoder 16. The X decoder 16 receives the address signals and decodes them to produce decoded row signals which are supplied onto row lines, which are connected to the memory array 20. The memory way 20 comprises an array of volatile memory cells arranged in a plurality of rows and columns. A reference control circuit 18 is connected to an array of reference non-volatile memory cells 21 and also controls the access of the array 21. The array of reference non-volatile memory cells 21 also comprise an array of reference memory cells arranged in a plurality of rows and columns. In the preferred embodiment, the reference memory cells in the array 21 of reference cells are the same type of non-volatile memory cells as those in the array 20 of memory cells. The array 21 is typically is outside of the main array 20 and is isolated from it physically. In addition, as is well known, a Y decoder 30, also for decoding, an address signal is positioned in the column direction and is used to control both the memory array 20 and the reference gray 21 (i.e. the Y decoder 30 includes a Y decoder for the main array 20 and a reference Y decoder for the reference array 21). From the output of the Y decoder 30, the column signals or sensed bit signals are supplied to a sense amplifier 32. As is well known, the sense amplifier 32 receives a signal from a selected memory cell from the memory array 20 and a signal from a selected reference cell from the reference array 21, and compares the two to determine the state of storage of the selected memory cell. Other well known components of the memory device 10 include an I/O buffer and controller 34 to receive the output signal from the sense amplifier 32. The memory device 10 further includes a logic controller 40, as well as other circuits necessary for the operation of the memory device 10, such as high voltage generation circuit 42 and a testing circuit 44.
There are a number of drawbacks of the memory device 10 shown in FIG. 1. Since the reference cells are separate from that of regular data cells, the reference cells do not track for example the affect of the process details of the data cells. Also the reference cells do not track the array environment of the data cells.
Accordingly, there is a need for a memory device having its memory cells and reference cells more integrated.